DFT Engineer

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Munich, Germany
Job Type
Direct Hire
Mar 29, 2018
Job ID
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In this highly visible role, you will be at the center of a chip design effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly. The ideal candidate will have 5+ years of DFT experience, leading DFT efforts for complex chip designs.
Job Description:
  • As a DFT engineer owning the complete DFT solutions in a chip design, you will have responsibilities spanning all aspects of chip design:
  • Working with chip DFT team to document DFT specifications and define the SOC test interface
  • Developing and implementing DFT architecture
  • Working with the validation team to verify DFT implementations and implement design changes
  • Generating structural test vectors, analyzing and improving coverage
  • Working with designers on STA, physical, power and logical issues
  • Working with test engineers to bring up test vectors on silicon
  • Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time.
  • Experience developing DFT specifications and driving DFT architecture and methods for designs.
  • Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools.
  • Knowledge of industry standards DFT and design tools.
  • Solid Understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon.
  • Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG/1500 related issues
  • Experience with STA constraints development and analysis for DFT modes and SDF simulations
  • Ability to conduct experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data.
  • MSEE or equivalent preferred
Identifier: $NEER